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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a preliminary technical data AD280 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 preliminary technical data universal multichannel industrial signal conditioning adc functional block diagram din0Cdin3 dout0C dout3 exc0 exc1 exc2 exc3 ain0 ain1 ain2 ain3 gnd snse agnd cjcin refin refout xtal2 xtal1 c2 c3 dgnd pgaout cint2 cint1 avdd dvdd drdy ce do di sk ptat ref pga xtal osc charge pump charge balance a/d c1 AD280 cpe iset xtal out alo reset input mux exc control logic features four input channels, with protection and switchable attenuation provision for cold junction sensor programmable excitation sources for rtd measure- ment and open input detection pga with programmable gains from 1 to 128 high resolution integrating a/d converter with pro- grammable integration period, up to 18-bit usable resolution 2.5 volt reference crystal oscillator charge pump circuit to allow single +5 v power serial interface compatible with most microcontrollers and microprocessors applications industrial data acquisition dcs (distributed control systems) plc (programmable logic controllers) general description the AD280 is a front-end integrated circuit for use in indus trial data acquisition applications. it has been specifically designed for the stringent requirements of industrial applications, with functions such as protection/protectability and high normal- mode rejection. the AD280 can be configured to accept up to four mv/v/tc inputs, or up to two rtd inputs (in 2-, 3- or 4- wire connection modes). the AD280 is not a stand-alone product, but is intended to be used with a companion microcontroller or microprocessor. descriptions of appropriate algorithms and control routines for this device are contained in this data sheet, as well as on a separate application note. the four primary input channels are designed for high input impedance for input signals up to 2.5 volts. each also con- tains a programmable input attenuator for input ranges up to 10 volts at reduced input impedance. the inputs contain inter- nal protection to allow for overload without affecting the accu- racy or operability of adjacent inputs. the input multiplexer also features a ground sense input and a separate input (with programmable excitation) for solid-state or thermistor tempera- ture sensors for cold junction compensation of thermocouples. an internal ptat (proportional to absolute temperature) sensor permits measurement of internal die temperature. the AD280 also offers four configurable excitation current sources. two of these sources can be configured to provide excitation for rtds, the amplitude of which can be set by an external resistor. all four excitation sources can be set to pro- vide +25 na or C25 na for use in detecting open inputs. the excitation sources are separately pinned out to allow for external protection devices to achieve very high normal-mode voltage protection. the input multiplexer feeds a programmable gain amplifier, with binary gains from 1 to 128. the pga drives a high resolu- tion integrating a/d converter, which is software programmable for integration time and can achieve usable resolution of up to 18 bits. the AD280 features a serial interface, operable to 10 mhz, and is compatible with a wide variety of microcontrollers and micro- processors. an onboard crystal oscillator and charge pump circuit are provided. the charge pump circuit, requiring just two external capacitors, provides the negative bias for this de- vice and allows full operation from a single +5 v supply. four general purpose digital outputs and four general purpose digital inputs are also provided; these may be used to implement external functions that may be required in some applications.
C2C rev. 0 AD280Cspecifications 1 preliminary technical data (@ t a = C25 8 c to +85 8 c, v dd = +5 v 6 10% unless otherwise noted) parameter min typ max units notes input characteristics input voltage range high impedance mode 3 3.5 v for linear operation without signal clipping in high impedance mode, pins ain0Cain3 attenuator mode 11 v for linear operation without signal clipping in attenuator mode, pins ain0Cain3 input impedance high impedance mode 20 m w pins ain0Cain3, also gnd sense and cjcin when jc excitation is disabled attenuator mode 70 100 130 k w pins ain0Cain3 bias current 1 na pins ain0Cain3, also gnd sense and cjcin when jc excitation is disabled bias current over temperature range 2 na pins ain0Cain3, also gnd sense and cjcin when jc excitation is disabled differential bias current 100 pa difference between perceived bias current at any input pin when selected input capacitance 7 pf pins ain0Cain3, also gnd sense and cjcin when jc excitation is disabled programmable gain amplifier pga gains 1 128 in binary steps gain ratio accuracy 0.1 0.3 %/fsr gain ratio temperature stability 5 ppm/ c fsr input offset voltage 10 50 m v input offset voltage temperature stability 2 5 m v/ c a/d converter conversion period 1 200 ms programmable, dependent upon crystal oscillator frequency resolution 32,000 counts @ t int = 16.66 ms, f clk = 12 mhz 100,000 counts @ t int = 200 ms, f clk = 12 mhz integral linearity 0.0015 0.003 % fsr including pga nonlinearity noise 4 counts @ t int = 100 ms, f clk = 12 mhz normal-mode rejection 92 db @ t int = 16.66 ms, f clk = 12 mhz 106 db @ t int = 100 ms, f clk = 12 mhz measurement latency 0 25 50 m s with c int = 4.7 nf (see note 1) nominal input span 2.5 3v input offset 100 m v see note 2 input offset drift 20 50 m v/ c see note 2 span error 0.5 % fsr see note 2 span drift 25 50 ppm/ c see note 2 excitation outputs output current excitation disabled 1 na exc0Cexc3 set for positive open circuit detection C20 C25 C30 na exc0Cexc3 set for negative open circuit detection 20 25 30 na exc0Cexc3 set for rtd excitation 0 2 ma exc0 and exc1 only, magnitude depends on value of external resistor temperature stability, rtd mode 35 ppm/ c exc0 and exc1 only, not including drift of external resistor reference output and input reference voltage 2.475 2.5 2.525 v reference voltage temperature stability 25 ppm/ c reference pin output current 1 ma excluding current required by refin pin digital levels input logic 0 voltage 0.8 v input logic 1 voltage 2 v output logic 0 voltage 0.45 v @ i = 1 ma output logic 1 voltage 2.4 v @ i = C60 m a
C3C rev. 0 AD280 preliminary technical data timing characteristics parameter min typ max units notes t cesk 50 ns chip enable to shift clock delay, or shift clock to chip enable setup t disu 20 ns data input setup time t skl 20 ns shift clock low time t skh 20 ns shift clock high time t dih 0 ns data input hold time t skdv 20 ns shift clock to data valid time t drel 20 ns data release time f clk 20 mhz clock speed parameter min typ max units notes ptat sensor (internal) voltage @ +25 c 0.475 v sensitivity 1.8 mv/ c integral linearity 2 c power supply v dd (analog and digital) 4.75 5 5.25 v i dd (analog) 2.5 3 ma i dd (digital) 1 1.5 ma with charge pump disabled a lo voltage C4 C5 C5.25 v with charge pump disabled notes 1 refers to the delay between receipt of a conversion command via the serial interface, and the actual start of the signal integr ation period. 2 in the intended modes of operation, as described in this data sheet and accompanying applications literature, these errors and drifts are reduced to negligible levels via firmware techniques. specifications subject to change without notice.
AD280 C4C rev. 0 preliminary technical data absolute maximum ratings* with respect parameter to min max units avdd agnd C0.3 +6.5 v avdd dgnd C0.3 +6.5 v dvdd agnd C0.3 +6.5 v dvdd dgnd C0.3 +6.5 v agnd dgnd C0.3 +0.3 v alo agnd C0.3 +6.5 v alo dgnd C0.3 +6.5 v ain0C3 agnd C12 +12 v exc0C3 agnd C12 +12 v refin agnd C0.3 avdd + 0.3 v din0C3 dgnd C0.3 dvdd + 0.3 v dout0C3 dgnd C0.3 dvdd + 0.3 v gnd sns, cjcin, refout, pgaout, iset, cint1C2, c1C3 agnd C0.3 +6.5 v cpe, xtal1C2, xtalout, reset, drdy, di, do, ce , sk dgnd C0.3 +6.5 v storage temperature C65 +150 c junction temperature +175 c lead temperature (soldering, 10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposu re to absolute maximum ratings for extended periods may effect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD280 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model temperature range package description package option AD280bs C25 c to +85 c 44-lead metric plastic quad flatpack (mqfp) s-44 AD280-eb evaluation kit pin configuration 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 pin 1 identifier top view (not to scale) nc = no connect cint1 pgaout agnd gnd sense cjcin refin refout ain3 ain2 ain1 ain0 dout0 dout1 dout2 dout3 c3 c2 dgnd c1 dvdd nc nc sk ce do di drdy din0 din1 cpe xtalout xtal1 xtal2 alo iset exc0 exc1 exc2 exc3 avdd din2 din3 reset cint2 AD280 thermal characteristics thermal resistance 44-lead mqfp q ja = 53.2 c/w q jc = 19 c/w
AD280 C5C rev. 0 preliminary technical data pin function description pin # pin name description 1 cpe charge pump enable. when tied to a logic 1, enables the internal charge pump within the AD280, allowing single supply operation. 2 xtalout buffered output from the crystal oscillator. 3 xtal1 connection for external crystal. 4 xtal2 connection for external crystal. 5 avdd positive power supply connection for analog circuit; nominally +5 v 5%. 6 alo negative power supply connection; tied externally to c3 (pin 38) nominally C5 v 5% supplied externally if charge pump is not used (see pin 1) 7 iset connection for external resistor, which sets the magnitude of the current used for rtd excitation. 8, 9, 10, 11 exc0Cexc3 excitation outputs used to supply open circuit detection current (all four) or rtd excitation current (exc0 and exc1 only). 12C15 ain0Cain3 analog input channels; single-ended inputs with respect to analog ground. 16 refout reference voltage output. nominally +2.5 v. 17 refin reference voltage input. nominally connected to refout. 18 cjcin cold junction compensation sensor input. can be connected to a thermistor or silicon tem- perature sensor for tc applications. 19 gnd sense ground sense input. used for measuring ground to compensate for ground loops or other offsets. 20 agnd analog ground. all input signals are referenced to this pin. 21 pgaout output of the programmable gain amplifier; supplied primarily for test and diagnostic purposes. 22, 23 cint1, cint2 connection for external integration capacitor; nominally 4.7 nf. 24 reset reset input to internal logic. when at logic 0, forces internal logic into the command mode condition. normally connected to a power-up reset circuit or rc reset circuit. 25C28 din3Cdin0 general purpose digital inputs, accessible via the serial interface. 29 drdy data ready output. when at logic 1, indicates that the most recent a/d conversion is com- plete and that data is available. this signal is also available via the serial interface, located in the status byte. 30 di data input for the serial interface. 31 do data output from the serial interface. in a three-state condition unless a data read command is being executed. 32 ce chip enable input. this signal is used to frame each byte of a command or data transfer. 33 sk shift clock input. this signal clocks data to/from the AD280 via the serial interface. 34C37 dout0Cdout3 general purpose digital inputs, accessible via the serial interface. 38 c3 connection for the shunt capacitor required by the charge pump circuit (nominally 1 m f/10 v tantalum, low esr (effective series resistance), negative terminal connected to pin 38). 39, 41 c2, c1 connections for the series capacitor required by the charge pump (nominally 1 m f/10 v tanta- lum, low esr (effective series resistance), negative terminal connected to pin 39). 40 dgnd digital ground. 42 dvdd power supply input for digital portion of the AD280. nominally +5 v 5%.
AD280 C6C rev. 0 preliminary technical data under program control, the inputs can be reconfigured as at- tenuated inputs. when enabled (by activating sw1 as shown in figure 2), the input impedance drops to approximately 100 k w , and the linear input range therefore expands to 10 volts via a 4:1 attenuator. using this provision, the AD280 can be used to measure signals of up to 10 volts without additional external components. a specialized esd protection circuit at each signal input pin will clamp at approximately 11 volts; protection for input voltages higher than this level can be achieved via the use of external series input resistors. table i. multiplexer control bits input pga2 pga1 pga0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 gnd sense 1 0 0 ptat 1 0 1 cjc 1 1 0 vref 1 1 1 the input multiplexer also provides inputs dedicated to measur- ing both analog ground and the reference voltage; these inputs are provided to facilitate the use of closed loop autocalibration algorithms. the ground sense input has an internal series resis- tor, in order to balance the effects of bias current at the inputs. the multiplexer also provides an input designed for use in cold junction compensation for thermocouple applications. this input has a programmable excitation source, providing appro- priate excitation for a 10 k w interchangeable thermistor. the excitation may be deactivated under digital control, allowing the input to be used for semiconductor temperature sensors such as the ad22100 or ad590. the multiplexer also connects to an internal ptat sensor, which may be used to sense and track the internal temperature of the die. while not practical for cold junction calibration pur- poses, this signal might be used for diagnostic purposes in some designs. oscillator the AD280 requires a clock signal for operating the internal charge balancing a/d converter, and for operating the optional internal charge pump used in single supply applications. the clock frequency affects the resolution of the a/d conversion process vs. the integration time; higher frequencies result in higher resolution. an internal oscillator allows for the connec- tion of a crystal, and optionally allows for an externally derived clock. the oscillator is a parallel resonant design known as a pierce oscillator, and is similar to those found on most microcontrollers. two external shunt capacitors are required to complete the circuit, as shown in figure 2. the value of the capacitors and the tolerance of the crystal affect clock speed accuracy, although very precise clock speed is not required in most applications. for crystals in the 10 mhz to 12 mhz range, 22 pf capacitors are usually appropriate. functional description the AD280 is a multifunction front end building block ic intended for applications in the industrial instrumentation and data acquisition fields. it contains an input multiplexer, pga, a/d converter, excitation sources and serial interface, all opti- mized for the measurement of rtds, thermocouples, volt and millivolt signals commonly found in industrial control environ- ments. when used with a microcontroller and the appropriate closed loop algorithms and firmware, the AD280 can support up to four thermocouple (or millivolt or voltage) inputs, or up to 2 rtds operating in either the 3-wire or 4-wire mode. the AD280 contains additional provisions for cold junction compen- sation of thermocouples, open lead detection and input protec- tion from normal-mode faults. figure 1 illustrates an example application, utilizing the AD280 along with a microcontroller to create a two-chip, four-channel industrial signal conditioner with serial communications. ch 0 ch 1 ch 2 ch 3 exc0 ain0 exc1 exc2 ain1 ain2 ain3 exc3 refin refout gnd sense ce sk din do xtalout AD280 4700pf 3.3 m f 16v 3.3 m f 16v 1 5dc txd rxd micro- controller (80c51, 68hc05, etc.) 1 2 1 2 1 2 1 2 figure 1. an example application input multiplexer the AD280 contains an input multiplexer primarily designed to support four input channels, along with additional channels for measurement of ground, reference, a cjc sensor and a built-in ptat signal. each of the input channels (ain0 through ain3) constitutes a high input impedance (>20 m w ) input for signals of up to 3 volts, with series limiting resistance and an active clamping structure. the input terminals are specifically de- signed to allow for input overloads of up to 11 volts without affecting the operation of any other channel. ainx mux 75k v 25k v sw1 figure 2. input attenuator structure
AD280 C7C rev. 0 preliminary technical data xtal1 xtal2 xtalout AD280 3 4 2 22pf (typ) 22pf (typ) to m controller xtal1 xtal2 xtalout AD280 3 4 2 to m controller from external clock figure 3. oscillator connections to drive the AD280 from an externally derived clock, xtal1 should be grounded, and the external clock should be applied to the xtal2 pin. the xtalout pin provides a buffered replica of the clock. this signal can be used to drive the clock input of a micro- controller, as shown in the applications diagram (figure 1). ground sense input the ground sense input is an analog input to the front end multiplexer, specifically designated for use in sensing (and thereby eliminating) ground offset errors in an AD280 applica- tion. while normally connected to agnd (pin 20), this input can be used for kelvin sensing at the reference terminal in- puts of an application. like the cjc input, this input is not designed for use as a field terminal input, and lacks the input protection features found in ain0 through ain3. in most ap- plications, the voltage on the ground sense input will be periodi- cally sampled, and the resulting data used to compensate the input signal data for offset. cold junction compensation input the AD280 provides an input explicitly for connection to a cold junction compensation temperature sensor. this input is a stan- dard input to the front end multiplexer, but with the addition of a programmable excitation designed for use with thermistor temperature sensors. when enabled, the input is connected to a 34.4 k w resistor (factory trimmed for value) which, in turn, is connected to the reference voltage. this kind of excitation is ideal for use with 10 k w nominal precalibrated thermistors such as the betatherm 10ka3. the 34.4 k w resistor serves to help linearize the ther- mistor voltage, although further digital linearization is required for most applications. when disabled, the excitation circuit is effectively disconnected from the input. this input may also be used with a wide variety of silicon tem- perature sensors, such as the ad590 or ad22100 series compo- nents, using the refout pin as a source of bias. furthermore, if no temperature sensor is required, this input may be used as an additional analog input for any desired purpose. this input does not exhibit the extended input voltage protection fea- tures found in ain0 through ain3. excitation current outputs the AD280 contains four excitation output pins programmable for excitation level. these pins are separate from the analog input pins to allow for the use of protection devices in envi- ronments with the possibility of high level normal-mode fault conditions. table ii. excitation control bits output msb lsb off 0 0 +25 na 0 1 C25 na 1 0 rtd 1 1 all four excitation outputs can be individually programmed (via the serial interface) to supply either +25 na or C25 na for use in open circuit detection. all four may also be individually dis- abled. exc0 and exc1 may also be programmed for a higher excitation current, the magnitude of which is determined by the value of the i set resistor attached to pin 7. these excitation sources are implemented as high impedance current sources, with compliance to 2.5 volts with respect to analog ground. in applications that do not require extended normal-mode voltage protection, they may simply be connected to their corresponding input signal pins (i.e., exc0 connects to ain0, exc1 to ain1, etc.) and will not interfere with signal measurement. setting the excitation current level the magnitude of the excitation current used for rtd sensors is set via a resistor connected between the i set pin and analog ground. this resistor sets the high level excitation magnitude for both exc0 and exc1, but has no effect on the open circuit detection current outputs of any of the exc pins. the formula for determining the approximate excitation current is: i exc = (2.5/ r iset ) 4 the temperature coefficient of the excitation current is directly affected by the tc of this resistor, so it is suggested that a high stability resistor (10 ppm/ c or less) be used. the total drift of the excitation source will not only include the drift of this resis- tor, but the reference drift as well. betatherm 10k v thermistor mux 34.4k v +v ref (switch enabled) mux 34.4k v +v ref (switch disabled) ref 1k v ad590 mux 34.4k v +v ref (switch disabled) ref out ad 22100 figure 4. cjc sensor connections
AD280 C8C rev. 0 preliminary technical data the excitation current level can be set for any value up to 2 ma; however, it is suggested that the lowest practical level be used to minimize self-heating and general power dissipation. a good value for most 100 w platinum or nickel rtd types is 250 m a; higher currents (up to 2 ma) are usually used only for copper rtds. if the high level excitation feature will not be used, this pin may be left open. auxiliary digital inputs and outputs the AD280 provides for four general purpose digital inputs, and four general purpose digital outputs. these inputs and outputs are accessed via the serial interface, and can be used for any desired purpose. some of the applications for these i/o pins include controlling external excitation circuits for specialized transducers, or for activating or monitoring other external devices. the general purpose outputs have a limited drive capa- bility, sufficient for driving cmos logic inputs; in some applica- tions it may be necessary to buffer these outputs with external devices. reference input and output the AD280 contains an internal bandgap reference voltage generator, the output of which is connected to pin 16 (refout). the reference is nominally +2.5 v. in most applications, it should be connected to refin, pin 17. for applications requir- ing better stability than that provided by the internal reference, the refout pin may be left unconnected and the refin pin may be driven from an external reference source such as the ad685. the refout signal may also be useful to drive external cir- cuitry in some applications. up to 1 ma may be drawn from this pin for external use. pga output the output of the programmable gain amplifier is brought out to this pin, primarily for the purposes of diagnostics and testing, although there may be applications where it can be utilized. the nominal output swing of this pin is 2.5 v, with a typical linear overrange capability to 3 v. external integration capacitor the charge balancing a/d converter within the AD280 requires an external integration capacitor, connected to cint1 and cint2 (pins 22 and 23). the nominal value of this capacitor is 4.7 nf. the value is not especially critical, so loose tolerance types ( 20%) may be employed. the dielectric characteristics of this capacitor have relatively little effect on the performance or accuracy of this type of a/d converter, so expensive film capaci- tors are unnecessary; inexpensive ceramic types (npo or x7r dielectrics) will suffice. reset input the reset input to the AD280 is used to initialize the state of the serial interface. when brought low, this signal will place the serial interface into a command state, where it is ready to accept a command. the reset input also has the effect of terminating an a/d conversion cycle in progress, and resetting the a/d converter control circuitry. this input may be driven from an external microcontroller supervisory circuit, or can be connected to a simple rc reset circuit. the reset input is not absolutely required, and is provided for convenience. if it is not used, the serial interface can be forced into the command state by shifting at least four consecu- tive bytes whose values are 0s into the di pin of the serial interface. the internal configuration registers can only be initial- ized through the interface, and are not cleared or reset by the reset pin. drdy (data ready) output pin the drdy pin indicates the state of the a/d converter. when low, it indicates that an a/d conversion is in progress; when high, it indicates that a conversion is complete, and that the data from the most recent conversion is available over the serial inter- face. this pin replicates a signal that is also available for inspec- tion via the serial interface; it is brought out as a separate pin in applications where it may be needed to trigger an interrupt. enhanced protection although the AD280 is designed to pr ovide protection to 10 volts beyond the power supply, there are many cases where signifi- cantly greater normal-mode overvoltage protection is required. the AD280 has been designed with this requirement in mind. when operated in the high impedance mode (i.e., for input signals limited to 3 volts), high normal-mode protection can be achieved through the use of large value series input resistors. the effect of the bias current present at the inputs to the AD280, working against a high external impedance, can be negated by balancing the inputs, i.e., always using a similarly valued resis- tance in series with the gnd sense input. r1 r2 + C ptc AD280 exc ain gnd sense figure 5. enhanced input normal-mode protection via large value in put and balancing resistors and ptc devices it should be noted, however, that when employing high value series input resistors, it is advisable to avoid extra capacitance directly at the input terminals. the pgas bias current is present at the inputs only when the multiplexer is addressed for that input; at other times, the input current falls to a negligible value, consisting of just the leakage current of the multiplexer itself. relatively low values of capacitance at the input terminals will therefore begin to slowly charge from the bias current when the channel is selected, and d ischarge through the sou rce impedance of the input signal when deselected. this charging/discharging behavior can cause large errors at very high gains. the excitation sources may also be protected via the use of a simple external circuit as shown in figure 5. in this example, a ptc (positive temperature coefficient) protection element is used to protect the excitation source. when used together with a high value external resistor to protect the input pin, complete protection for a universal input (tc, rtd, mv or v) can be afforded.
AD280 C9C rev. 0 preliminary technical data charge pump the AD280 contains an internal charge pump circuit, which eliminates the need for a negative power supply voltage. the charge pump operates at 1/64th of the clock frequency. because of clock noise and the high current spikes generated by any charge pump, it can be expected that the use of the charge pump will somewhat degrade the performance (accuracy and resolu- tion) of the AD280; for the most stringent and demanding ap- plications, an external negative supply is preferred. the charge pump requires the use of two external capacitors, as shown in figure 6. one of these capacitors is a shunt element, and is connected from pin 38 to ground. the other is a series element, and is connected between pin 39 and pin 41. these capacitors should be low esr tantalum types for the lowest supply ripple and best performance; standard tantalum types, or most aluminum types, should be avoided. a suggested capacitor value is 3.3 m f, although the charge pump is unconditionally stable, and larger values may be used. + 41 39 6 38 3.3 m f 16v + c1 c2 alo c3 AD280 3.3 m f 16v figure 6. charge pump connections interface examples figure 7 is an example of how the AD280 can be configured to accept an array of input configurations for thermocouples, rtds, millivolt and voltage inputs. in this example, the excita- tion sources are connected in such a way that just exc0 and exc1 would be enabled for the rtd interconnect, but all four could be enabled at the +25 na or C25 na level for open lead detection. although not shown, it would also be quite possible to connect a single rtd and two other single-ended inputs, such as thermocouples, millivolt or voltage signals. serial peripheral interface the AD280 features a serial peripheral interface (spi) that enables bidirectional half duplex communication with a micro- controller or microcomputer. the interface consists of five signals: ce chip enable (active low) di data input do data output sk shift clock drdy data ready since the do pin will always be three-stated, except during a read command, it may be tied to di (data input) in applica- tions where the microcontroller or other interface circuitry can be operated bidirectionally. the drdy signal is a duplication of the drdy bit in the status byte. it is provided as an external pin in applications where a signal is required to generate an interrupt at the end of the con- version cycle. rtd rtd tc0 tc1 tc2 tc3 cjc sensor exc0 exc2 exc1 exc3 gnd snse agnd cjcin ain0 ain1 ain2 ain3 AD280 figure 7. example of universal input connection arrangement for the AD280
AD280 C10C rev. 0 preliminary technical data all communications with the AD280 are composed of byte transfers. each byte transfer is bracketed by the dropping of the ce line, and the sk input is used to shift data in and out of the device. input data is clocked in on the rising edge of sk, and output data is valid at the falling edge of sk. note that sk must be high at both the rising and falling edges of ce . there are six write registers and four read registers within the AD280, as shown in figure 10. to initiate a communica- tion sequence, the microcontroller, which contains a 4-bit com- mand code, writes a command byte to the AD280. the AD280 command register (cmd) is the first of the six write registers. it will be loaded with the 4-bit command code that determines the type of communication, and the number of bytes in the communication sequence. table iii shows the possible command codes. after reset, the AD280 will be in command mode, where it expects to receive a command byte from the microcontroller. if the command code specifies a write sequence, the microcontroller will then transmit one or more parameter bytes to the AD280. if the command code specifies a read sequence, the microcontroller will receive one or more parameter bytes from the AD280. the only exception is the start conversion command code, which requires no data bytes. an undefined command code will be treated as a nop (no operation) and ignored. t dih t disu t cesk t skl t skh t cesk ce sk di don't care don't care don't care cmd3 cmd2 cmd1 cmd0 msb lsb don't care don't care do t skdv t drel figure 8. read cycle t dih t disu t cesk t skl t skh t cesk ce sk di don't care don't care don't care start bit cmd3 cmd2 cmd1 cmd0 msb lsb don't care figure 9. write cycle if a communications sequence is interrupted, the AD280 may get stuck waiting for a data transfer that never occurs. there are two ways to force the AD280 back into command mode: one is to activate the reset in signal and the other is to write four consecutive bytes with all bits set to 0. there are five write registers which constitute configuration parameters. the two lowest bytes (cfg0 and cfg1) contain the 16-bit binary integer value that determines the length of integration time for a/d conversions. the next byte, cfg2, contains four bits to control the input attenuation for each chan- nel and four bits to drive the auxiliary digital output signals. cfg3 contains three bits to control the multiplexer, three bits to control the programmable gain amplifier, and one bit for cjc excitation. cfg4 contains eight bits to control the excitation sources. when written, the contents of these bytes will be latched and will hold their values until overwritten with new values. at power-up, the contents of these latches will be undefined. they must be loaded before an a/d conversion can be performed. any attempt to write to these latches during the course of an a/d conversion will cause the conversion to be aborted. the write cycle will, however, be considered valid and the data will be latched.
C11C rev. 0 AD280 preliminary technical data table iii. command codes and corresponding functions command code cc3 cc2 cc1 cc0 function parameter 0000no operation none 0001 read status 1 0010 read data0 1 0011 read data1 1 0100 read data2 1 0101 read data0/data1/data2 3 0110no operation none 0111no operation none 1000write cfg0 1 1001write cfg1 1 1010write cfg0/cfg1 2 1011write cfg2 1 1100write cfg3 1 1101write cfg4 1 1110write cfg2/cfg3/cfg4 3 1111 start conversion none the four read registers in the AD280 consist of three data bytes (data0, data1, data2) and a status byte. the three data bytes constitute a 24-bit twos-complement binary integer that is proportional to the signal data. the status byte contains the auxiliary digital input data, along with an image of the drdy signal, which is a copy of the separate external drdy line. the data bytes and status byte may be read at any time. if read during an a/d conversion, the data bytes will contain the results of the last conversion completed. they will not be updated with the new conversion data until the next conversion is com- plete. the user is responsible for reading the data when it is valid. the data is valid after one conversion is complete (i.e., when drdy goes high), and remains valid until the next con- version is complete. the data must be read early enough in the conversion cycle to assure that it is not updated during the data transfer. normally, it is most efficient to use the follow- ing sequence: na na na na msb lsb cmd: cmd code 3 cmd code 2 cmd code 1 cmd code 0 cjc exc pga2 msb lsb cfg4: pga1 pga0 mux2 mux1 mux0 d out 3 msb lsb cfg3: d out 2 d out 1 d out 0 atten ch3 atten ch2 atten ch1 atten ch0 exc3 hi msb lsb cfg2: exc3 lo exc2 hi exc2 lo exc1 hi exc1 lo exc0 lo exc0 hi t int msb bit 14 msb lsb cfg1: bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 msb lsb cfg0: t int lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 din 3 drdy na na na msb lsb status: din 2 din 1 din 0 data msb bit 22 msb lsb data2: bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 msb lsb data1: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 msb lsb bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 data lsb data0: na writeable registers readable registers figure 10. AD280 internal registers 1. wait for the conversion to complete. 2. set the configuration parameters for the next conversion. 3. wait for settling of the mux and pga (1 ms max). read the data from the previous conversion while waiting. 4. trigger the a/d for the next conversion. all AD280 registers may be read or written in a single byte mode by using the appropriate commands. in the single byte mode, the command code specifies which individual register is to be read or written. the byte must be read or written immedi- ately after the command code is sent to the AD280. in addition to byte-at-a-time access, multiple byte mode allows certain register combinations to be read or written with- out the need to transmit a command byte for each register. the command code specifies the number of bytes that follow. up to three bytes of data, in ascending order, may be transferred after the command byte. this capability substantially reduces the time required to access the AD280, since in most cases the register groupings will always be read or written together. it is important to note that in all cases, regardless of whether single or multiple byte mode is used, each byte transferred will require the complete sequence of the ce (chip enable) and sk (shift clock) pins. setting the a/d integration period the integration period of the AD280s a/d converter is set by writing to the config0 and config1 registers. these two bytes constitute a 16-bit binary integer which represents the upper 16 bits of a 21-bit counter clocked by the AD280s clock. the formula for the integration period is: d config0/1 = ( f clk t int )/32 where d config0/1 represents a 16-bit integer. for example, when using a 10 mhz clock frequency, and when an integration period of 16.666 ms is desired, the required integer is 5209 10 , or 1459 16 . practical integration periods range from 1 ms to 200 ms, depending upon clock speed.
AD280 C12C rev. 0 c3032C8C4/98 printed in u.s.a. preliminary technical data 44-lead metric plastic quad flatpack (mqfp) (s-44) top view (pins down) 12 44 1 11 22 23 34 33 0.45 (0.018) 0.3 (0.012) 13.45 (0.529) 12.95 (0.510) 8.45 (0.333) 8.3 (0.327) 10.1 (0.398) 9.90 (0.390) 0.8 (0.031) bsc 2.1 (0.083) 1.95 (0.077) 0.23 (0.009) 0.13 (0.005) 0.25 (0.01) min seating plane 0 min 2.45 (0.096) max 1.03 (0.041) 0.73 (0.029) the accuracy of the integration period is limited by the clock speed and resolution of the config0/1 registers; faster clock frequencies will result in more accurate integration periods, with corresponding improvement in normal mode rejection. a/d resolution the resolution of the a/d converter is dependent upon the integration period and the clock speed. for a given integration period, the nominal full-scale output of the a/d will be 50% of the number of clock cycles that occur in the integration period. for example, a cl ock speed of 10 mhz and an integra- tion period of 10 ms will produce an output of approximately 50,000 counts. all ranges have an overrange capability of (typically) 20%, so the a/d will typically remain linear up to 60,000 counts (in the example just illustrated). the exception to this overrange capability is when the attenuators are used to achieve a 10 v input range; in this case, the special esd circuits will clamp the input at approximately 11 volts, thereby reduc- ing the overrange to 10%. evaluation kit an evaluation kit, consisting of an evaluation board with an AD280 and support components is available (part number AD280-ed). this kit includes a software demo program written to operate under windows ? 95. windows is a registered trademark of microsoft corporation. outline dimensions dimensions shown in mm and (inches).

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